Technical Lead Engineer — Network Validation & Characterization

Meta's Infrastructure team delivers scalable and reliable custom ASIC solutions to meet Meta's data center needs. Ramping to production and solving data center scaling and deployment challenges requires a systems-based approach to silicon bring-up and validation. The team works on productization: early architecture and design inputs, pre-silicon validation on emulation platforms, first-silicon bring-up, and post-silicon characterization across process, voltage, and temperature corners. We write tests, build bare-metal environments and reusable frameworks that scale from pre-silicon platforms to large fleets of ASICs in the lab, and we build and maintain extensive lab automation to do it at volume and velocity. Responsibilities
Own the end-to-end validation and characterization strategy for Meta custom silicon programs in your domain, from pre-silicon emulation through post-silicon bring-up and PVT characterization Define the test plan: measurement and benchmarking methodology, instrumentation, functional and performance coverage, corner coverage across process/voltage/temperature, and pass/fail criteria Establish and document best practices for measurement rigor, accuracy, and correlation across bench, emulation, and ATE/production data Drive validation of domain feature sets (power or networking) on emulation platforms pre-silicon and on real silicon post-silicon Review schematics, power delivery networks, high-speed interface designs, and board/platform configurations with hardware and design teams; provide early design and debuggability inputs Write and review automation and analysis code that scales characterization from a single bench to many units in the lab Lead debug of complex cross-stack issues — silicon, firmware, driver, board, thermal, and fabric/switch layers — and drive root cause to closure with design, software, hardware, ODM, and vendor partners Provide technical guidance and planning for a team of validation engineers; mentor engineers and improve standards for data quality and rigor Partner with manufacturing, production, and data center teams to transfer characterization learnings into production screens and fleet health monitoring Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 12+ years of relevant industry experience Demonstrated hands-on validation and characterization experience on complex ASICs, SoCs, NICs, or high-speed interfaces Proven experience with PVT (Process / Voltage / Temperature) characterization Ability to read and reason about schematics and either power delivery networks or high-speed interface implementations Proficiency in Python for test development, lab automation, and/or data analysis Hands-on lab experience with domain-relevant instrumentation Experience taking a custom NIC or networking ASIC from first silicon through high-volume production Experience working directly with ODMs and silicon/IP vendors Hands-on lab experience with domain-relevant instrumentation for Networking - traffic generators, protocol analyzers, high-speed scopes/BERTs, optics and cabling, switches; plus RDMA (RoCE and/or InfiniBand) at the protocol and debug level, Ethernet performance tooling (iperf, netperf, packet capture and analysis), and both front-end and back-end NICs and their differing traffic and scaling models Experience with Linux networking internals, kernel/userspace drivers, and DPDK or verbs-level programming Advanced degree (MS or PhD) in Electrical Engineering, Computer Engineering, or a related field Familiarity with SerDes tuning, link margining, FEC, and errata characterization Experience building large-scale lab automation frameworks and characterization data pipelines Experience with AI/HPC back-end fabrics and collective communication traffic patterns