Senior Principal Engineer, Chip Lead, Photonic Fabric Chiplet

Location

Santa Clara, CA

Level

Staff / Principal

Department

—

Type

Full-Time

Salary

$182,360 - $273,200

Job Description

Posted on:

June 9, 2026

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. The Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ includes optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact.

What You Can Expect

Marvell Technology is

seeking

a highly experienced

Chip

Lead

 to own the

end

‑

end

development of a heterogeneous photonic chiplet

comprising

high

‑

speed

electrical IC with advanced analog SERDES

 and a

photonic integrated circuit (PIC)

, brought together using

advanced

‑

packaged

technologies

This role requires technical breadth across

mixed

‑

signal

SoC design, photonic integration,
chiplet

‑

style

partitioning,
firmware
and
package

‑

level

‑

design

, along with proven leadership delivering complex silicon from concept through

silicon

bring

‑

, ATE, and system validation

The ideal candidate has shipped

high

‑

speed

I/O and/or optical products

, understands

electrical

‑

optical

tradeoffs, and can act as the single technical owner across die, package, optics, and system boundaries.

Key Responsibilities

Own the
end
‑
to
‑
end product
design
s
panning
Electrical IC
, Photonic IC,
f
irmware stack
,
and
a
dvanced packaging
design.

Lead
micro
‑
architecture
and RTL development
 for
the Electrical IC
that
can
include
high speed SERDES
and digital subsystems with
internally developed
IPs
and
industry standard
external I
Ps such as
UALink
, UCIe
,
etc.

Collaborate
with
v
erification team to
ensure robust functional and per
formance verification
spanning
digital RTL,
AMS
and electrical-optical interface
s
.

Work closely
with
physical design
and packaging teams on
floorplanning
, physical implementation, timing,
power, and
physical verifi
cation closure.

Partner
with DFT experts to
d
rive
DFT strategy
 for digital, analog SERDES, and system
‑
level testability.

Partner
with
p
hotonics
teamto define
PIC architecture
, interfaces, and control schemes
,
and
e
nsure robust
electrical
-optical
co
‑
design
.

Collaborate
with test engineering to drive
ATE enablement
, test program development, and debug.

Lead
cross-functional team to
complete
system
‑
level validation
, including boards, optics, firmware, and software interaction.
Drive
root
‑
cause analysis across silicon, package, optics, and system domains
.
Mentor
and developsenior engineers and influence
cross functional teams
across disciplines
in a matrixed environment
.

Identify
and
communicate technical status, risks, and tradeoffs to engineering and product leadership.

What We're Looking For

Bachelor’s degree in
Computer Science
,
Electrical Engineering
,
or
related fields and 15+
years of related
professional experience
OR
Master’s degree
/
PhD
in
Computer Science,
Electrical
Engineering
or
related fields with
8
-12
years of experience.

15+ years of experience in
ASIC / SoC development
with
end
‑
to
‑
end
chip ownership
.

Strong experience across
Micro
‑
architecture
and RTL desig
n,
h
igh
‑
speed
analog SERDE
S
,
p
hysical design and
sign
‑
off
,
DFT and manufacturing test
,
a
dvanced packaging and
chiplet
‑
style
integration
,
p
ost
‑
silicon
bring
‑
up
, ATE, and system validation
.

Ability to
clearly articulate architectural and
implementation
tradeoffs
 across performance, power, area, yield, cost, schedule, and risk.

Strong
track record
of
driving alignment
across
cross
‑
functional
teams with differing viewpoints in a matrixed environmentand drive solutions to toughengineering problems across the product stack.

Excellent written and verbal communication skills, including leading technical reviews and communicating status, risks, and decisions to engineering and product leadership
at the executive level
.

While deep
expertise
across all domains is not expecte
d, t
he ideal candidate will
demonstrate
the
maturity and
technical judgment to
foster a culture of cross
-domain collabor
ation
and
deal with conflicts in a c
alm and constructive
fashion.

Preferred Qualifications

P
rior experience in
delivery of
high
‑
speed
I/O and/or optical products
 into production.

Prior
experienceas
Chip
Lead, SoC Architect, or
System
‑
Level
Technical Lead
.

Expected Base Pay Range (USD)

182,360 - 273,200, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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