Silicon Failure Analysis Lead

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As Silicon Failure Analysis Lead, you will help integrate SOC technologies into mobile phones, tablets and laptops. You will work with different product disciplines (Design, Product, Test, Process Technology, Yield, Quality and Reliability) to accurately determine the root cause of failures, with the aim of developing advanced, high quality, cost effective and reliable Individual Contributor (ICs).

The Failure Analysis (FA) lead will be responsible for all aspects of failure analysis with respect to Silicon Quality and Reliability Engineering activities, engaging in debug activities from the silicon to the entire package. As a technical leader, you will collaborate with cross-functional teams to drive end-to-end Failure Analysis for yield, reliability and field failures. You will have experience in all aspects of failure analysis: ATE and system level testing, diagnostics, Design for Test (ATPG/MBIST), curve tracing, non-destructive analysis (3D X-ray, CSAM, optical inspection), sample preparation, Electrical FA (Photon/Thermal Emission and Laser-based techniques) and Physical Failure Analysis.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 10 years of experience in SoC (System on Chip) Failure Analysis.
• Experience operating failure analysis equipment for performing Electrical Fault Isolation (EFI) and using Automated Test Equipment (ATE) with data from Design for Test (DFT) diagnosis tools.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience with Siemens Tessent tools for Design for Test (ATPG, MBIST, diagnosis) and ATE platforms such as Advantest 93k.
• Experience modifying digital test programs and test patterns for failure analysis debug.
• Experience with scripting languages such as Python, C, or Java.
• Experience collaborating with wafer fabrication or OSAT (Outsourced Semiconductor Assembly and Test) vendors.

• Drive yield, reliability, and return merchandise authorization (RMA) failure analysis through fault isolation and physical failure analysis.
• Lead systematic efforts to eliminate yield detractors, accelerate yield ramps, reduce defective parts per million (DPPM), and lower operational costs.
• Collaborate with external foundry partners and OSATs to align and enable upstream and downstream yield learning.
• Deliver investigative insights back to design and layout teams to support robust Design for Yield (DFY) practices and manufacturing ramps.
• Oversee the operational readiness and safety compliance of the regional failure analysis laboratories.

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 10 years of experience in SoC (System on Chip) Failure Analysis.
• Experience operating failure analysis equipment for performing Electrical Fault Isolation (EFI) and using Automated Test Equipment (ATE) with data from Design for Test (DFT) diagnosis tools.