Principal Photonics Package Architect

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Principal 

Photonics

Package Architect

About the Role

Astera Labs is seeking a Principal Photonics Package Architect to define and drive package architecture for next-generation photonics products for scale up and scale out AI infrastructure applications. This is a high-impact senior individual contributor role focused on aligning electrical, thermal, and mechanical design requirements across functions, enabling robust package implementation, and guiding package technology decisions for NPO and CPO products.

Responsibilities

• Define

  photonics

  package architecture,

  define

  electrical

  and optical

  interface specifications, and

  establish

  signal integrity

  and power integrity

  requirements.

• Establish and manage Thermal Design Power (TDP) budgets and thermal performance targets.

• Drive cross-functional alignment with EIC, PIC, and hardware teams on co-design constraints

  and drive system optical link budget

  .

• Partner with validation, test, and reliability teams to define DFT and DFR requirements and acceptance criteria.

• Finalize bump map and ball

  map, and

  manage ECOs and revision control of package design databases.

• Lead package-level design reviews and own the package design technical roadmap.

Basic Qualifications

• B.S., M.S., or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Physics, or a related field.

• 10+ years of experience in semiconductor

  or

  photonics

  package development, package design, or package integration, with

  demonstrated

  technical leadership.

• Strong understanding of package architecture tradeoffs across electrical,

  optical,

  thermal, mechanical, and manufacturability considerations.

• Experience working across chip, board, and system-level design

  electrical and optical

  interfaces in complex product development environments.

• Experience with package EDA tools and electrical simulation tools, including Cadence APD+ and Ansys HFSS.

• Experience with advanced packaging design, including 2.5D and 3D package architectures.

• Familiarity with package design flows, design database management, and engineering change control practices.

• Ability to drive technical decisions, resolve cross-functional issues, and communicate architecture direction clearly to stakeholders.

• Strong foundation

  in design reviews, risk assessment, and design quality from concept through production release.

Preferred Qualifications

• Experience with industry-standard

  optical

  interfaces and interconnect technologies relevant to package design.

• Experience with advanced

  photonics

  packaging technologies for

  data center interconnects

  .

• Experience supporting package bring-up and correlating design assumptions with validation results.

• Experience supporting cross-functional design closure with silicon, photonics, board, validation, test, and reliability teams.

• Knowledge of package design for NPO or CPO products.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.