Physical Design Engineer - Multiple Levels
Location
Santa Clara, CA
Level
Mid-Level
Department
Semiconductors
Type
Salary
$140,000 - $230,000
Job Description
Posted on:
2026-05-05
Responsibilities
- Innovate and develop complex, high-speed, low power designs.
- Manage the complete Physical Design Flow and deliveries.
- Conduct floorplanning, power planning, and IR drop analysis.
- Perform timing optimization and closure, and debug timing violations.
- Implement timing fixes and functional ECOs.
- Conduct formal verification and physical verification.
- Utilize scripting and software languages for design verification.
Job Requirements
- Bachelor's degree in Science, Engineering, or related field with 4+ years of experience, or a Master's degree with 3+ years, or a PhD with 2+ years of experience.
- Experience in Physical Design and Place & Route tools (Cadence Innovus/Synopsys Fusion Compiler).
- Timing closure experience in Synopsys PTSI.
- Knowledge of power domain analysis and physical verification.
- Strong scripting skills in Python, PERL/TCL, and Linux/Unix shell.
- Understanding of functional and test mode constraints.
- Ability to debug and fix physical violations.
