Physical Design Engineer - Multiple Levels
Location
Santa Clara, CA
Level
Mid-Level
Department
Semiconductors
Type
Salary
$140,000 - $230,000
Job Description
Posted on:
2026-03-23
Responsibilities
- Innovate and implement chips and cores using advanced tools and technologies.
- Manage the complete Physical Design Flow for complex designs.
- Develop low power implementation methods and customized Place & Route solutions.
- Conduct power planning, IR drop analysis, and cell placement.
- Optimize timing closure and debug timing violations for designs.
- Perform formal verification and physical verification tasks.
- Utilize scripting and software languages for design verification and delivery.
Job Requirements
- Bachelor's, Master's, or PhD in Science, Engineering, or related field.
- 2-10+ years of experience in Physical Design and ASIC development.
- Experience with Place & Route tools like Cadence Innovus or Synopsys Fusion Compiler.
- Proficiency in timing closure and formal verification processes.
- Knowledge of power domain analysis and physical verification techniques.
- Familiarity with scripting languages such as Python, PERL/TCL, and Linux/Unix shell.
- Strong understanding of design constraints and methodologies in ASIC design.
