RTL & Codesign Engineer
Location
San Francisco, CA
Level
Senior-Level
Department
Consumer Electronics
Type
Salary
$225,000 - $445,000
Job Description
Posted on:
2026-03-07
Responsibilities
- Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems.
- Contribute to architectural studies including performance modeling and feasibility analysis.
- Collaborate with software, simulator, and compiler teams for hardware/software co-design.
- Partner with DV and PD to ensure functional correctness, timing closure, and area/power targets.
- Build and review performance and functional models to validate design intent.
- Participate in design reviews, documentation, and bring-up support across the silicon lifecycle.
- Engage in cross-functional collaboration with architecture, ML systems, compilers, and verification teams.
Job Requirements
- Graduate-level research or industry experience in computer architecture and AI/ML hardware–software co-design.
- Expertise in writing production-quality RTL in Verilog/SystemVerilog.
- Experience in developing hardware design models or architectural simulators for AI/ML systems.
- Familiarity with industry-standard design tools and methodologies.
- Strong problem-solving skills and ability to think across abstraction layers.
- Passion for building industry-leading massive-scale hardware systems.
- Ability to comply with U.S. export control laws and regulations.
