Physical Design Engineer
Location
Cupertino, CA
Level
Mid-Level
Department
Consumer Electronics
Type
Salary
$147,000 - $272,000
Job Description
Posted on:
2026-01-16
Responsibilities
- Generate block/chip level static timing constraints.
- Build full chip floor-plan including pin placement, partitions, and power grid.
- Develop and validate low power clock network guidelines.
- Perform block level place and route to meet timing, area, and power constraints.
- Generate and implement ECOs to address timing, noise, and EM IR violations.
- Run Physical Design verification flow and provide guidelines for fixing LVS/DRC violations.
- Participate in establishing CAD and physical design methodologies for correct by construction designs.
Job Requirements
- Deep design experience in high PHY and/or SOC designs.
- Knowledge of industry standards in Physical Design, including synthesis, floor-planning, and place & route.
- Experience in developing Power-grid and Clock specifications.
- Strong understanding of Physical construction, Integration, and Physical Verification.
- Knowledge of Basic SoC Architecture and HDL languages like Verilog.
- Proficiency in scripting languages such as Perl/Tcl and understanding of Extraction and STA methodology.
- Understanding of Physical Design Verification methodology to debug LVS/DRC issues.
