Physical Design Engineer
Location
San Francisco, CA
Level
Entry-Level
Department
Consumer Electronics
Type
Salary
$147,000 - $272,000
Job Description
Posted on:
2026-03-14
Responsibilities
- Generate block/chip level static timing constraints.
- Build full chip floor-plan including pin placement, partitions, and power grid.
- Develop and validate high-performance low power clock network guidelines.
- Perform block level place and route and close the design to meet timing, area, and power constraints.
- Generate and implement ECOs to fix timing, noise, and EM IR violations.
- Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations.
- Participate in establishing CAD and physical design methodologies for correct by construction designs.
Job Requirements
- Deep design experience in high PHY and/or SOC designs.
- Knowledge about industry standards and practices in Physical Design.
- Experience in developing and implementing Power-grid and Clock specifications.
- Strong understanding of Physical construction, Integration, and Verification.
- Knowledge of HDL languages like Verilog for timing fixes.
- Understanding of scripting languages such as Perl/Tcl and Physical Design Verification methodology.
- Ability to debug LVS/DRC issues at chip/block level.
