Physical Design Engineer
Location
Sunnyvale, CA
Level
Mid-Level
Department
Consumer Electronics
Type
Salary
$180,000 - $320,000
Job Description
Posted on:
2026-01-27
Responsibilities
- Generate block/chip level static timing constraints.
- Build full chip floor-plan including pin placement, partitions, and power grid.
- Develop and validate high-performance low-power clock network guidelines.
- Perform block level place and route to meet timing, area, and power constraints.
- Generate and implement ECOs to address timing, noise, and EM IR violations.
- Run Physical Design verification flow at chip/block level and guide other designers to fix LVS/DRC violations.
- Assist in establishing CAD and physical design methodologies for correct by construction designs.
Job Requirements
- Deep design experience in high PHY and/or SOC designs.
- Knowledge of industry standards in Physical Design, including synthesis, floor-planning, and Place & Route.
- Experience in developing Power-grid and Clock specifications.
- Strong understanding of Physical construction, Integration, and Verification.
- Knowledge of HDL languages like Verilog for collaboration with the logic design team.
- Proficiency in industry standard Physical Design & Synthesis tools.
- Understanding of scripting languages such as Perl/Tcl and Physical Design Verification methodology.
