Physical Analysis Engineer
Location
Cupertino, CA
Level
Entry-Level
Department
Consumer Electronics
Type
Salary
$181,000 - $272,000
Job Description
Posted on:
2026-02-26
Responsibilities
- Work on timing implementation and closure for ASIC chips.
- Develop and enhance timing-related scripts for critical path analysis.
- Support full chip and block level constraints for multiple timing modes.
- Own timing and signal integrity closures for SoCs and I/O interfaces.
- Develop and maintain methodology and flows related to timing verification and closure.
- Collaborate with cross-functional teams to resolve complex timing issues.
- Manage full chip and block level timing closure throughout the project cycle.
Job Requirements
- Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field.
- 2 years of experience in the job offered or related occupation.
- Experience in physical design and STA tools.
- Knowledge of semiconductor and timing constraints.
- Familiarity with System-on-Chip (SoC) design.
- Commitment to inclusion and diversity in the workplace.
- Ability to work in a fast-paced, team-oriented environment.
