RTL & Co-design Engineer (junior)
Location
San Francisco, CA
Level
Entry-Level
Department
Consumer Electronics
Type
Salary
$225,000 - $445,000
Job Description
Posted on:
2026-02-12
Responsibilities
- Produce clean, production-quality microarchitecture and RTL for accelerator subsystems.
- Contribute to architectural studies, including performance modeling and feasibility analysis.
- Collaborate with software, simulator, and compiler teams for hardware/software co-design.
- Partner with DV and PD for functional correctness and timing closure.
- Build and review performance and functional models to validate design intent.
- Participate in design reviews, documentation, and support across the silicon lifecycle.
- Engage in problem-solving across abstraction layers from algorithms to circuits.
Job Requirements
- Graduate-level research or industry experience in computer architecture or AI/ML hardware-software co-design.
- Expertise in writing production-quality RTL in Verilog/SystemVerilog.
- Experience developing hardware design models or architectural simulators for AI/ML systems.
- Familiarity with industry-standard design tools and methodologies.
- Ability to work cross-functionally with various engineering teams.
- Strong problem-solving skills.
- Passion for building large-scale hardware systems.
