RTL & Co-design Engineer (junior)
Location
San Francisco, CA
Level
Entry-Level
Department
Consumer Electronics
Type
Salary
$250,000 - $460,000
Job Description
Posted on:
2026-01-22
Responsibilities
- Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems.
- Contribute to architectural studies including performance modeling and feasibility analysis.
- Collaborate with software, simulator, and compiler teams for hardware/software co-design.
- Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.
- Build and review performance and functional models to validate design intent.
- Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.
Job Requirements
- Graduate-level research or industry experience in computer architecture, AI/ML hardware-software co-design.
- Expertise in writing production-quality RTL in Verilog/SystemVerilog.
- Experience developing hardware design models or architectural simulators, ideally for AI/ML systems.
- Familiarity with industry-standard design tools and methodologies.
- Strong problem-solving skills and ability to think across abstraction layers.
- Passion for building industry-leading massive-scale hardware systems.
