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Digital Design Engineer Intern

Job Description

Posted on: 
2025-11-01

Responsibilities

  • Participate in RTL development using SystemVerilog
  • Participate in Micro-architecture, Design, and Verification reviews and provide feedback
  • Analyze design and enhance PPA (Power, Performance, Area)
  • Support Verification to analyze and improve Verification Coverage
  • Debug simulations

Job Requirements

  • Currently pursuing a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field
  • Knowledge of Verilog or SystemVerilog
  • Knowledge of Logic Design Fundamentals
  • Must obtain work authorization in the country of employment
  • Preferred experience with Lint, Synthesis, Timing Closure, Formal Verification, or Physical Design tools
  • Experience with scripting languages (Python, Perl, TCL, shell scripting)
  • Intent to return to degree-program after the internship/co-op
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