Engineer / Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560)
Location
Austin, TX
Level
Mid-Level
Department
Semiconductors
Type
Salary
$106,000 - $162,000
Job Description
Posted on:
2025-05-17
Responsibilities
- Complete entire physical implementation of the block level and tapeout production chip
- Block level floorplan analysis
- Customized Clock tree structure and Place & Route
- Implement ECOs for timing closure
- Conduct Signal EM/Noise and Power IR/EM analysis and fixes
- Perform DRC/LVS/ERC/ANTENNA analysis and cleanup
- Physical verification sign-off
Job Requirements
- Master’s degree in Electrical/Computer Science Engineering with 3+ years of experience, or Bachelor’s degree with 5+ years
- Experience in Netlist (or RTL)-GDS physical implementation
- In-depth knowledge of major EDA tools/design flows
- Experience with TSMC N16 technology or below
- Experience in block level implementation or chip integration and signoff
- Proficiency in Perl/TCL programming
- Ability to work regularly at a Customer site in North Austin, TX area
