Texas Instruments

Packaging Engineering Intern - MS/PhD - Santa Clara

Job Description

Posted on: 
2025-09-19

Responsibilities

  • Participate in cross-functional teams for semiconductor packaging technology development.
  • Work on various packaging technologies including Wirebond, Flip Chip, and Modules.
  • Conduct mechanical, thermal, and electrical characterization of packaging advancements.
  • Collaborate with team members across different functions.
  • Analyze processes, assembly, reliability, and materials related to semiconductor packaging.
  • Manage time effectively to ensure on-time project delivery.
  • Build strong, influential relationships within the team.

Job Requirements

  • Currently pursuing a Master's degree in Mechanical Engineering, Materials Science, Chemical Engineering, Physics, or Electrical Engineering.
  • Cumulative GPA of 3.0/4.0 or higher.
  • Knowledge of semiconductor packaging processes and materials preferred.
  • Strong analytical and problem-solving skills.
  • Excellent written and verbal communication skills.
  • Ability to work effectively in a fast-paced environment.
  • Initiative and drive for results.
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