Semiconductor Packaging Engineering Intern - Fall 2025

The Semiconductor Packaging Engineering Intern will assist packaging engineers in defining and validating packages for new products, potentially working in labs for tests and mechanical analysis, and collaborating with design teams using CAD.

• Work with packaging engineers to define and validate packages for new products.
• Perform tests and mechanical analysis to evaluate packaging and materials.
• Collaborate with the design team using CAD for package definitions.
• Model package performance (thermal, mechanical, electrical) with the Package Innovation team.
• Address and solve design, materials, and processing issues during development.
• Utilize MS Office tools for documentation and presentation.
• Learn and apply fundamental engineering concepts to practical problems.

• B.S, M.S. or Ph.D. Candidate in Materials Science, Mechanical Engineering, or Electrical Engineering.
• Positive attitude, self-driven, and good communication skills.
• Willingness to learn new concepts and apply knowledge.
• Working knowledge of MS Office tools (PowerPoint, Word, Excel).
• Familiarity with CAD tools and/or Finite Element Simulation tools is a plus.
• Knowledge of various IC packages and soldering is a plus.
• Understanding of Statistical Data Analysis and Design of Experiment is a plus.