Design Verification Engineer

The role is for a Design Verification Engineer at Mega Cloud Lab, responsible for developing and executing verification environments for digital designs.

• Design and implement verification environments using SystemVerilog and UVM.
• Develop simulation models and testbenches.
• Apply verification methodologies for high functional coverage.
• Analyze simulation results and debug design issues.
• Collaborate with design engineers to enhance design quality.
• Stay updated with the latest verification tools and methodologies.

• Proficiency in SystemVerilog and UVM.
• Experience in digital design and verification methodologies.
• Familiarity with industry-standard verification tools.
• Strong problem-solving and analytical skills.
• Excellent communication and teamwork abilities.