Low Power ASIC Engineer - New College Grad 2025
Location
Santa Clara, CA
Level
Full-Time
Department
Consumer Electronics
Type
Salary
Job Description
Posted on:
2025-05-07
Responsibilities
- Collaborate with Low Power Architecture, Design, and Software teams to understand next-generation features.
- Architect and develop testbench, infrastructure, and test plans for verifying power management solutions.
- Improve power-aware design verification methodologies.
- Influence EDA vendors to enhance simulation and debug efficiencies.
- Utilize knowledge of low power design techniques in the development process.
- Engage in debugging using tools like Verdi.
- Write and maintain scripts or Makefiles for simulation programs.
Job Requirements
- Pursuing or recently completed a BS, MS, or PhD in Electrical or Computer Engineering.
- Strong background or understanding of low power architectures and verification.
- Familiarity with low power design techniques such as multi VT, clock gating, and DVFS.
- Proficiency in Verilog, SystemVerilog, and understanding of UVM.
- Experience with Incisive Low-Power or Synopsys VCS NLP.
- Scripting abilities in Python or PERL are a plus.
- Knowledge of C or C++ is an advantage.
