ASIC Design Engineer - New College Grad 2025
Location
Westford, MA
Level
Full-Time
Department
Consumer Electronics
Type
Salary
Job Description
Posted on:
2025-03-06
Responsibilities
- Micro architecting the next generation of PCIE Physical and Data-Link layers.
- Implementing high-performance, area, and power-efficient RTL designs.
- Collaborating with architects, partners, software engineers, and circuit designers.
- Partnering with the Physical Design team on partitioning, floorplanning, and timing closure.
- Providing design documentation and debugging functional and performance issues.
- Supporting integration and infrastructure development.
- Ensuring compliance with performance, adaptability, and safety industry standards.
Job Requirements
- Bachelor’s Degree in Electrical Engineering, Computer Science, or Computer Engineering.
- Experience in coding PCIE Physical/Data-Link Layer logic.
- In-depth understanding of physical design.
- Proficiency in Verilog or System Verilog.
- Strong collaboration and communication skills.
- Knowledge of PCIe PL/DL sub-blocks and alternate protocol negotiation (CXL/UCIe).
- Experience with post-silicon bringup and understanding of signal integrity concepts.
