Design Verification Engineer
Location
Melbourne, FL
Level
Entry-Level
Department
Consumer Electronics
Type
Salary
Job Description
Posted on:
2026-01-27
Responsibilities
- Study design specifications and create test plans.
- Develop infrastructure in SystemVerilog/UVM to stress the design.
- Develop and fix failures from regressions, close bugs.
- Use LLMs to perform verification efficiently.
- Develop verification plans for features and implement them.
- Track and report DV progress using various metrics.
- Create scalable and portable test-benches.
Job Requirements
- Strong knowledge of OOP, SystemVerilog, and UVM.
- Experience with verification methodologies and tools.
- Some working experience using LLMs for efficiency and quality.
- Knowledge of scripting languages such as Python, Perl, or TCL.
- Familiarity with power-aware verification methodologies (UPF) is a plus.
- Experience with serial and parallel protocols is a plus.
- Knowledge of formal verification and emulation technologies is a plus.
