Design Verification Engineer (University Grad)
Location
Sunnyvale, CA
Level
Full-Time
Department
Software Development
Type
Salary
$114,000 - $133,000
Job Description
Posted on:
2025-01-28
Responsibilities
- Define verification plans for core IP or SoCs with researchers and architects.
- Track detailed test plans for various modules and top levels.
- Drive Design Verification to closure based on verification metrics.
- Debug and resolve functional failures in design with the Design team.
- Collaborate with cross-functional teams to ensure design quality.
- Develop continuous improvements in Design Verification methodologies and tools.
Job Requirements
- Bachelor's degree in Computer Science, Computer Engineering, or related field (or in progress).
- Experience in System Verilog, C, C++.
- Familiarity with verification methodologies like UVM.
- Proficiency in EDA tools and scripting languages (Python, TCL, Perl, Shell).
- Strong problem analysis and solution identification skills.
- Experience in cross-group collaboration.
- Preferred: Experience with revision control systems and verification of ARM/RISC-V based sub-systems or SoCs.
